Data storage device and parity code processing method thereof

ABSTRACT

A data storage device and a parity code processing method thereof are provided. The data storage device includes a non-volatile memory and a controller. The controller includes a RAID ECC engine. The RAID ECC engine has a memory, wherein after completing an encoding operation on each N pages of user data to generate a corresponding parity code. The RAID ECC engine compresses the parity code and stores the compressed parity code in the memory, wherein after all K parity codes of the K×N pages of the user data are compressed and stored in the memory, the RAID ECC engine writes the compressed K parity codes to the non-volatile memory. As such, the frequency of switching the state of the RAID ECC engine is reduced, and the number and time of writing data to the non-volatile memory is reduced.

FIELD OF THE INVENTION

The present invention relates to a data storage device, and moreparticularly to a data storage device and a parity code processingmethod thereof.

BACKGROUND OF THE INVENTION

Generally, a data storage device is composed of a controller and anon-volatile memory such as a flash memory, and the controller mayinclude a redundant array of independent disks (RAID) error correctingcode (ECC) engine. The RAID ECC engine is mainly used to perform errorcorrection procedures. One of the operating principles is that when ahost wants to write user data to the non-volatile memory and the writtenuser data uses page as the management unit, the controllersimultaneously sends the user data to the RAID ECC engine for encodingoperation until the user data of a page group, for example, the userdata of page 0 to page N-1 is encoded. After that, the RAID ECC enginewill generate a parity code corresponding to the user data of page 0 topage N-1, and then write the parity code into the non-volatile memory,that is, the parity code can be used as the data of page N, wherein N isa positive integer greater than 1. Therefore, after the user data ofeach N pages is encoded, the RAID ECC engine will switch its state tooutput the encoded parity code to the non-volatile memory by eachencoding operation. This makes the parity code written to thenon-volatile memory not continuous and also lower the writingefficiency.

SUMMARY OF THE INVENTION

In view of the above, an object of the invention is to provide a datastorage device and a parity code processing method thereof. To achievethe above object, an embodiment of the invention provides a data storagedevice, including a non-volatile memory and a controller electricallycoupled to the non-volatile memory. The controller includes an accessinterface, a central processing unit (CPU) and a RAID ECC engine. TheRAID ECC engine has a memory, wherein after completing the encodingoperation on each N pages of the user data to generate a correspondingparity code, the RAID ECC engine compresses the parity code and storesthe compressed parity code in the memory of the RAID ECC engine, whereinafter all K parity codes of the K×N pages of the user data arecompressed and stored in the memory, the RAID ECC engine writes thecompressed K parity codes to the non-volatile memory, wherein K and Nare both positive integers greater than one.

In addition, an embodiment of the invention further provides a paritycode processing method, which is implemented in the controller of theforegoing embodiment, and includes the following steps. First,configuring the CPU to issue at least one control signal to the RAID ECCengine and transmitting the user data of a plurality of pages to theRAID ECC engine. Second, configuring the RAID ECC engine to perform anencoding operation on the user data of N pages based on the controlsignal to generate a corresponding parity code, compress the paritycode, and store the compressed parity code in a memory of the RAID ECCengine. Then, configuring the CPU to determine whether the user data ofa super page group has been transmitted to the RAID ECC engine, whereinthe user data of the super page group is referred to as the user data ofK×N pages. When it is determined that the user data of the super pagegroup has been transmitted to the RAID ECC engine, configuring the CPUto control the RAID ECC engine to write the compressed K parity codes ofthe user data of the super page group to the non-volatile memory.

In order to further understand the features and technical contents ofthe present invention, please refer to the following detaileddescription and the accompanying drawings of the invention. However, thedescription and the drawings are merely illustrative of the inventionand are not intended to limit the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more readily apparent to thoseordinarily skilled in the art after reviewing the following detaileddescription and accompanying drawings, in which:

FIG. 1 is a schematic functional block diagram of a data storage deviceaccording to an embodiment of the invention;

FIG. 2 is a schematic functional block diagram of a RAID ECC engine inthe data storage device of FIG. 1;

FIG. 3A to FIG. 3D are schematic diagrams of the RAID ECC engineperforming a parity code processing method according to FIG. 2;

FIG. 3E is a schematic diagram of a stored written data in thenon-volatile memory in FIG. 1 storing the written data under theembodiments of FIG. 3A to FIG. 3D;

FIG. 3F is a schematic timing diagram of the operational circuits inFIG. 3A to FIG. 3D performing the parity code processing method; and

FIG. 4 is a schematic flow diagram of a parity code processing methodaccording to an embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In the following, the invention will be described in detail byillustration of various embodiments of the invention. However, theconcept of the invention may be embodied in many different forms andshould not be construed as being limited to the illustrative embodimentsset forth herein. In addition, the same reference numerals used in thedrawings may represent similar elements.

First, please refer to FIG. 1. FIG. 1 is a schematic functional blockdiagram of a data storage device according to an embodiment of theinvention. The data storage device 1 includes a non-volatile memory 110and a controller 120. In the embodiment, the non-volatile memory 110includes a plurality of blocks (not shown). Each block further includesa plurality of pages, and the page is the smallest unit of program. Thatis, the page is the smallest unit for data writing or reading, and aword line can control more than one page. In addition, the block is thesmallest unit for data erasing. Therefore, the blocks can be classifiedinto spare blocks, active blocks and data blocks according to theirfunctions. The spare blocks are the blocks that can be selected andwritten the data to, the active blocks are the blocks that already beselected and written the data to, and the data blocks are the blockswhere the data is finish written and can no longer be written. It shouldbe noted that the invention does not limit the specific implementationmanner of the blocks and the pages, and those skilled in the art shouldbe able to perform related designs according to actual needs orapplications. In addition, in the embodiment, the non-volatile memory110 is preferably implemented by a flash memory, but the invention isnot limited thereto.

The controller 120 is electrically coupled to the non-volatile memory110 and is used to control data access in the non-volatile memory 110.It must be understood that the data storage device 1 is usually usedtogether with a host 2 to write user data into the non-volatile memory110 or read the user data from the non-volatile memory 110 according tothe write/read command issued by the host 2. Therefore, in theembodiment, the controller 120 preferably is a flash memory controllerand may mainly include a CPU 124, an access interface 121 and a RAID ECCengine 123. In addition, the CPU 124 preferably has its own memory, suchas a CPU memory 1241 for storing temporary data. In order to facilitatethe following description, in the embodiment, the CPU 124 and the CPUmemory 1241 are separately drawn. However, it should be understood bythose of ordinary skill in the art that the CPU memory 1241 is actuallyencompassed within the CPU 124. Incidentally, since the CPU memory 1241usually has a fixed size, the CPU 124 will store the temporary data toan external memory outside the controller 120 as long as the temporarydata stored by the CPU 124 is larger than the available space of the CPUmemory 1241. However, the speed of which the CPU 124 accesses theexternal memory is much slower than the speed of which the CPU accessesthe internal memory, so that the overall system performance is likely todecline.

The access interface 121 is coupled to the host 2 and the non-volatilememory 110. The CPU 124 is used to interpret write/read commands issuedby the host 2 to generate operation commands and control the accessinterface 121 to access the user data of the non-volatile memory 110based on the operation commands. In addition, in the embodiment, thecontroller 120 can further include a data buffer 122 coupled to theaccess interface 121, the RAID ECC engine 123, and the non-volatilememory 110, and is used to temporarily store the user data from the host2 or the non-volatile memory 110. However, in addition to the user data,the data buffer 122 can also preferably be used to temporarily storein-system programming (ISP) or logical-to-physical address mapping tablerequired for the operation of the CPU 124, but the invention is notlimited thereto. In addition, in the embodiment, the data buffer 122 ispreferably implemented by a static random access memory (SRAM) or arandom access memory (RAM) capable of fast access, but the invention isnot limited thereto.

The RAID ECC engine 123 is coupled to the data buffer 122 and thenon-volatile memory 110 and is used to perform an error correctionprocedure on the user data. In this embodiment, the operation principleof the error correction procedure refers to exclusive OR (XOR) logicaloperations and can be divided into an encoding operation or a decodingoperation according to the functions. Therefore, in FIG. 1, differentoperation paths will be represented by different chain lines, and itshould be understood that the decoding operation provides function suchas error detection and correction, or data recovery. In addition, in theembodiment, the RAID ECC engine 123 preferably also has its own memory,such as the RAM 1231. Specifically, after completing the encodingoperation on each N pages of the user data (or so called the user dataof each page group) to generate a corresponding parity code, the RAIDECC engine 123 compresses the parity code and stores the compressedparity code in the RAM 1231. After all K parity codes of the K×N pagesof the user data are compressed and stored in the RAM 1231, the RAID ECCengine 123 writes the compressed K parity codes to the non-volatilememory 110, wherein K and N are both positive integers greater than one.It should be noted that, in the embodiment, the RAID ECC engine 123 mayalso write the compressed K parity codes into the data buffer 122, andthen write the compressed K parity code into the non-volatile memory 110through the data buffer 122. In summary, the invention does not limitthe specific implementation manner in which the RAID ECC engine 123writes the compressed K parity codes to the non-volatile memory 110, andthose of ordinary skill in the art should be able to make relevantdesigns based on actual needs or applications.

According to the above teachings, those of ordinary skill in the artshould understand that the user data of the K×N pages refers to the userdata of the K page groups, or it is simply referred to as user data of asuper page group in the embodiment. In addition, if the management unitof the user data is a sector instead of a page, for example, a page mayinclude a plurality of sectors, the RAID ECC engine 123 also compressesthe parity code and stores the compressed parity code in the RAM 1231after completing the encoding operation on the user data of each sectorgroup to generate the corresponding parity code. After the K paritycodes of the user data of the K sector groups are compressed and storedin the RAM 1231, the RAID ECC engine 123 writes the compressed K paritycodes to the non-volatile memory 110. Since the data management methodsof the sector and page are similar, only the example of the page will bedescribed below, but the invention is not limited thereto.

In contrast, when the controller 120 needs to read the user data fromthe non-volatile memory 110, the controller 120 reads the user data ofthe page according to the preset read parameters and performs the errorcorrection by using other error correction codes (e.g., a low densityparity check (LDPC) code) on the read user data of the page. When thecontroller 120 reads the user data of a certain page of the super pagegroup (e.g., the user data of the page 1) but the LDPC code cannotcorrect the error, the controller 120 may read the user data of page 0,page 2 to page N-1 and the compressed parity codes corresponding to theuser data of page 0 to page N-1 from the non-volatile memory 110, andthen send them to the RAID ECC engine 123 to perform the decodingoperation, wherein the data obtained by the decoding operation is thecorrect user data of the page 1. Since the operation of the encoding ordecoding operation of the user data by the RAID ECC engine 123 is wellknown to those of ordinary skill in the art, no redundant detail is tobe given herein.

In summary, compared with the prior art, the RAID ECC engine 123 of theembodiment reduces the amount of data by compressing the parity code andstores the compressed parity code in the RAM 1231 first, instead ofimmediately writing a parity code to the non-volatile memory 110 foreach encoding operation. After a plurality of parity codes of the userdata of an entire super page group are compressed and stored in the RAM1231, the RAID ECC engine 123 writes the compressed plurality of paritycodes to the non-volatile memory 110 in one time. Thereby, the frequencyof switching the state of the RAID ECC engine 123 is reduced and thenumber and time of writing the parity code to the non-volatile memory110 are reduced, so as to relatively increase the service life of thenon-volatile memory 110. In addition, since the compression of paritycode can reduce the amount of data actually written to the non-volatilememory particles, the embodiment can achieve the effect of reading andwriting acceleration.

On the other hand, in addition to using the RAM 1231 for storing thecompressed parity code, the RAID ECC engine 123 also uses the RAM 1231for temporary storage of the operation values when the RAID ECC engine123 performs the encoding operation or the decoding operation. The sizeof the RAM 1231 can be, for example, 64 KB, but the RAID ECC engine 123may need only 16 KB or 32 KB of memory space to operate according toactual needs, such as page size, parity code size, or numbers of pathsused. Therefore, when the memory space of the RAM 1231 is not fullyused, the data storage device 1 of the embodiment can also map theunused memory space of the RAM 1231 to the CPU memory 1241. That is, theunused memory space of the RAM 1231 is shared, and the unused memoryspace address of the RAM 1231 is mapped to the memory space address ofthe CPU memory 1241 to be virtualized as part of the CPU memory 1241. Asshown by the slanted line block in FIG. 1, the memory space of the CPUmemory 1241 is substantially extended (expanded). As such, the CPU 124can also utilize the unused memory space of the RAM 1231 to storetemporary data. In other words, the temporary data can be stored in theRAM 1231 of the RAID ECC engine 123 in addition to the CPU memory 1241and need not to be stored in the external memory outside the controller120. As such, the frequency of access the external memory by the CPU 124is reduced and the overall system performance is improved.

Next, the implementation of the RAID ECC engine 123 of the embodimentwill be further described below. Please also refer to FIG. 2. FIG. 2 isa schematic functional block diagram of the RAID ECC engine in the datastorage device of FIG. 1. The components in FIG. 2 and the samecomponents as those in FIG. 1 are labeled with the same numbers, so noredundant detail is to be given herein. In the embodiment, the RAID ECCengine 123 mainly includes a state machine 220, a selector 230, acontrol register 240, and M+1 operational circuits 210_0 to 210_M,wherein M is a positive integer greater than 1. Each of the operationalcircuits 210_0 to 210_M includes an XOR logical operation unit, a pagebuffer, and a first selector. For example, the operational circuit 210_0includes an XOR logical operation unit 211_0, a page buffer 212_0, and afirst selector 213_0, and so on, and the operational circuit 210_Mincludes an XOR logical operation unit 211_M, a page buffer 212_M, and afirst selector 213_M. It can be understood that the state machine 220,the selector 230, the control register 240, the XOR logical operationunits 211_0 to 211_M, and the first selectors 213_0 to 213_M may beimplemented by a pure hardware circuit or by a hardware circuit withfirmware or software, but the invention is not limited thereto.

In the embodiment, the control register 240 is coupled to the CPU 124and used to receive at least one control signal from the CPU 124 and thetemporary data. In addition, in order to facilitate the followingdescription, the embodiment will be first described with only one of theoperational circuits, for example, the operational circuit 210_0.However, those skilled in the art should be able to understand theprinciple of the other operational circuits 210_1 to 210_M. As shown inFIG. 2, the first selector 213_0 has two input ends 0 and 1 and anoutput end. The two input ends 0 and 1 of the first selector 213_0 arerespectively coupled to an output end of the XOR logical operation unit211_0 and the control register 240. The output end of the first selector213_0 is coupled to the page buffer 212_0. In the embodiment, the CPU124 can control (set) a selection end (sel) of the first selector 213_0by the control register 240 to select the input end 0 as the inputsource of the page buffer 212_0 to input data, so the input data at thistime is the operation result (not shown) of the XOR logical operationunit 211_0, and the operation result can be stored in the page buffer212_0.

In contrast, the CPU 124 can also control (set) the selection end (sel)of the first selector 213_0 by the control register 240 to select theinput end 1 as the input source of the page buffer 212_0 to input data.Therefore, the input data at this time is changed to the temporary data(not shown) from the CPU 124 provided by the control register 240, andthe temporary data can also be stored in the page buffer 212_0. That is,the RAM 1231 in FIG. 1 can be composed, for example, by the page buffers212_0 to 212_M in FIG. 2. When the operational circuit 210_0 does notperform encoding or decoding operations or even is not used to store thecompressed parity code (i.e., the page buffer 212_0 of the operationalcircuit 210_0 is not used), the CPU 124 can control the first selector213_0 so that the input end 1 of the first selector 213_0 serves as aninput source of the page buffer 212_0. As such, the unused page buffer212_0 can be used to store temporary data from the CPU 124, therebyachieving another object of the present invention, which is to have theCPU 124 share the RAM 1231 of the RAID ECC engine 123.

In addition, the state machine 220 is coupled to the control register240 and is used to control whether the RAID ECC engine 123 performsencoding or decoding operations or enters an idle or done state. Inaddition, the state machine 220 can further assist the control register240 to control (set) the selection ends of the first selectors 213_0 to213_M to determine the input sources of the page buffers 212_0 to 212_M,and assist the control register 240 to control the selection end (sel)of the selector 230 to determine its output interface. In theembodiment, the selector 230 has M+1 output ends and an input end. TheM+1 output ends of the selector 230 are respectively coupled to theinput ends of the operation circuits 210_0 to 210_M, and the input endof the selector 230 is coupled to the data buffer 122 or thenon-volatile memory 110. Therefore, in the embodiment, the CPU 124 canalso control (set) the selection end (sel) of the selector 230 by thecontrol register 240 so that the user data received by the input end ofthe selector 230 can be outputted to the designated operational circuits210_0 to 210_M to perform subsequent encoding or decoding operations. Insummary, the control register 240 is not only used to control (set) theselection ends of the first selectors 213_0 to 213_M, but also tocontrol (set) the selection end (sel) of the selector 230 and is alsoused to control the operation of the state machine 220. In practice, thefirst selectors 213_0 to 213_M of the operation circuits 210_0 to 210_Mcan preferably be respectively implemented by multiplexers (MUX), andthe selector 230 is preferably implemented by a demultiplexer (DeMUX),but the invention is not limited thereto.

Next, please refer to FIG. 3A to FIG. 3E. FIG. 3A to FIG. 3D are used toexplain in detail the operation principle of the parity code processingmethod performed by the RAID ECC engine 123. FIG. 3E is a schematicdiagram of the stored written data in the non-volatile memory 110 inFIG. 1 under the embodiment of FIG. 3A to FIG. 3D. It should be notedthat in the embodiment of FIG. 3A to FIG. 3D, it is first assumed thatboth K and N are 3 for the following description, but it is not intendedto limit the invention. As shown in FIG. 3A, when the host 2 is to writethe user data to the non-volatile memory 110, the CPU 124 temporarilystores the user data from the host 2 in the data buffer 122, and thenthe user data is transmitted to the RAID ECC engine 123 via the databuffer 122. Then, the CPU 124 sets the control register 240 to triggerthe state machine 220 to instruct the RAID ECC engine 123 to perform theencoding operation on the user data. Then, the control register 240controls the selector 230 so that the user data received by the inputend of the selector 230 from the data buffer 122 (e.g., the user data ofpage 0 to page 2) is outputted to the operational circuit 210_0 via theoutput end 0 of the selector 230. At the same time, the control register240 sets the selection end (sel) of the first selector 213_0 of theoperational circuit 210_0 to “0”, so that the XOR logical operation unit211_0 of the operation circuit 210_0 can perform an encoding operation(XOR logical operation) on the user data outputted by the selector 230and the encoded data temporarily stored in the page buffer 212_0. Then,the operation result (new encoded data) is outputted to the page buffer212_0 to replace the originally stored encoded data (old encoded data).According to the above procedure, the operation circuit 210_0 cansequentially receive the user data of the page 0 to page 2 transmittedby the data buffer 122, and then perform the encoding operation on theuser data of the page 0 to page 2 by the XOR logical operation unit211_0 to obtain the parity code P0 of a page size. As such, the encodingoperation on the user data of the first page group is completed.

Then, the RAID ECC engine 123 can write the parity code P0 via the pagebuffer 212_0 to the page buffer (e.g., the page buffer 212_M) used bythe compression/decompression circuit 250 and start the compressionfunction, so that the page buffer 212_M stores the compressed paritycode P0. In summary, the invention does not limit the specificimplementation of the compression/decompression circuit 250 and the wayit compresses the parity code P0. Moreover, the above-mentioneddescription in which the operational circuit 210_0 is adopted to performthe encoding operation on the user data of the first page group and thepage buffer 212_M is used by the compression/decompression circuit 250are merely an example, and is not used to limit the invention. The CPU124 can determine which operational circuit is to perform the encodingoperation on the user data of the first page group according to actualneeds or applications, and determine which page buffers are used by thecompression/decompression circuit 250. It can be understood that, in theembodiment, the RAID ECC engine 123 further includes compression anddecompression functions. Moreover, after the parity code P0 is writtento the page buffer 212_M used by the compression/decompression circuit250 and the compression is started, the CPU 124 can switch to output theuser data received by the input end of the selector 230 to other unusedoperational circuits, such as the operational circuit 210_1, therebyperforming the encoding operation on the user data of the second pagegroup.

Therefore, as shown in FIG. 3B, the control register 240 controls theselector 230 so that the user data of page 3 to page 5 received by theinput end of the selector 230 from the data buffer 122 is outputted tothe operational circuit 210_1 via the output end of the selector 230. Atthe same time, the control register 240 sets the selection end (sel) ofthe first selector 213_1 of the operational circuit 210_1 to “0”, sothat the operational circuit 210_1 can sequentially receive the userdata of the page 3 to page 5 transmitted by the data buffer 122, andthen perform the encoding operation on the user data of page 3 to page 5by the XOR logical operational unit 211_1 to obtain the parity code P1of a page size. As such, the encoding operation on the user data of thesecond page group is completed. Then, the RAID ECC engine 123 canfurther write the parity code P1 via the page buffer 212_1 to the pagebuffer 212_M used by the compression/decompression circuit 250 and startthe compression function, so that the page buffer 212_M also stores thecompressed parity code P1. Similarly, after the parity code P1 iswritten to the page buffer 212_M used by the compression/decompressioncircuit 250 and compression is started, the CPU 124 can again switch tooutput the user data received by the input end of the selector 230 toother unused operational circuits, such as the operational circuit210_2, thereby performing the encoding operation on the user data of thethird page group.

As shown in FIG. 3C, the control register 240 controls the selector 230so that the user data of page 6 to page 8 received by the input end ofthe selector 230 from the data buffer 122 is outputted to theoperational circuit 210_2 via the output end 2 of the selector 230. Atthe same time, the control register 240 sets the selection end (sel) ofthe first selector 213_2 of the operational circuit 210_2 to “0”, sothat the operational circuit 210_2 can sequentially receive the userdata of the page 6 to page 8 transmitted by the data buffer 122, andthen perform the encoding operation on the user data of page 6 to page 8by the XOR logical operational unit 211_2 to obtain the parity code P2of a page size. As such, the encoding operation on the user data of thethird page group is completed. Then, the RAID ECC engine 123 can furtherwrite the parity code P2 via the page buffer 212_2 to the page buffer212_M used by the compression/decompression circuit 250 and start thecompression function, so that the page buffer 212_M also stores thecompressed parity code P2.

Finally, as shown in FIG. 3D, the compressed parity code using the superpage group as the configuration only needs to share the same page.Therefore, after the parity codes P0 to P2 of the user data of theentire super page group have been compressed and stored in the pagebuffer 212_M, the RAID ECC engine 123 can write the compressed paritycodes P0 to P2 to the non-volatile memory 110 via the page buffer 212_Mat one time. As such, the RAID ECC engine 123 does not need to switchthe state in the intermediate process to individually output each paritycode P0 to P2. As described above, it is understood that the RAID ECCengine 123 can also write the compressed parity codes P0 to P2 into thedata buffer 122 first, and then write the compressed parity codes P0 toP2 to the non-volatile memory 110 via the data buffer 122, but theinvention is not limited thereto.

It is noted that, in the embodiment of FIG. 3E, it is assumed that thenon-volatile memory 110 stores the written data by using a blank page ofone of the blocks B0 to B3, and each block B0 to B3 is placed in achannel, for example, block B0 is placed in channel CH#0, block B1 isplaced in channel CH#1, and so on, and block B3 is placed in ChannelCH#3. In addition, the data may be sequentially written to the blankpages of the blocks B0 to B3, or may be written in parallel to the blankpages of the blocks B0 to B3, and the invention is not limited thereto.Therefore, when the controller 120 is to write the user data of page 0to page 8 to the non-volatile memory 110, the user data of page 0 can bestored in the first blank page of the block B0, the user data of page 1can be stored in the first blank page of block B1, and so on, the userdata of page 7 can be stored in the second blank page of block B3, andthe user profile of page 8 can be stored in the third blank page ofblock B0. After the parity codes P0 to P2 of the user data of page 0 topage 8 have been compressed and stored in the page buffer 212_M, thecompressed parity codes P0 to P2 are then written to the third blankpage of the block B1 via the RAID ECC engine 123, as shown in FIG. 3E.

According to the above content, it is known that writing the user dataof page 0 to page 3 to the first blank page and writing the user data ofpage 4 to page 7 to the second blank page belong to writing the userdata to the blank page, instead of writing a parity code P0 or P1 to ablank page. Therefore, the controller 120 can directly write the userdata to the blank page without waiting for the generation of the paritycode P0 or P1, and thereby the user data can be written to thenon-volatile memory 110 at the fastest speed. Of course, the inventiondoes not limit that the compressed parity codes P0 to P2 can only bewritten to the third blank page of the block B1. The RAID ECC engine 123(or the controller 120) can decide to write the compressed parity codeP0 to P2 to which blank page of which block according to actual needs orapplications. In other words, in the other embodiments, the blocks B0 toB3 can be further divided into two areas (not shown), that is, a dataarea and a parity code area. Therefore, the controller 120 may firstwrite the user data to the blank page of the data area, and the RAID ECCengine 123 then writes the compressed parity code to the blank page ofthe parity code area. Alternatively, after the controller 120 firstfills the data area with the user data, the RAID ECC engine 123 writesthe compressed parity code to the blank page of the parity code area,but the invention is not limited thereto.

In addition, please refer to FIG. 3F. FIG. 3F is a schematic timingdiagram of the operational circuits in FIG. 3A to FIG. 3D performing theparity code processing method. As shown in FIG. 3F, after the paritycode of the user data of the current page group is written to the pagebuffer 212_M used by the compression/decompression circuit 250 and thecompression is started, the CPU 124 can switch to output the user datareceived by the input end of the selector 230 to other unusedoperational circuits to perform the encoding operation on the user dataof the next page group. Therefore, the compression processing of theprevious parity code and the encoding operation of the user data of thenext page group can be processed in parallel, as such, the overallsystem performance is not degraded.

Furthermore, in order to further explain the operation flow of the datastorage device 1 processing the parity codes P0 to P2, the inventionfurther provides an embodiment of the parity code processing method.Therefore, please also refer to FIG. 4, which is a schematic flowdiagram of a parity code processing method according to an embodiment ofthe invention. It should be noted that the parity code processing methodof FIG. 4 can be performed by the controller 120 of the data storagedevice 1, especially by the CPU 124 and the RAID ECC engine 123 of thecontroller 120, but the invention does not limit the parity codeprocessing method of FIG. 4 to be executed only by the controller 120 inFIG. 1. As shown in FIG. 4, in step S410, the CPU 124 issues at leastone control signal to the RAID ECC engine 123. Thereafter, in step S420,the CPU 124 transmits the user data of a plurality of pages, forexample, the user data of N pages, to the RAID ECC engine 123. Asdescribed above, in the embodiment, the CPU 124 temporarily stores theuser data from the host 2 in the data buffer 122, and transmits the userdata to the RAID ECC engine 123 via the data buffer 122.

Thereafter, in step S430, the RAID ECC engine 123 performs the encodingoperation on the user data of the N pages to generate a correspondingparity code according to the control signal. Thereafter, in step S440,the RAID ECC engine 123 compresses the parity code and stores thecompressed parity code in the RAM 1231. Thereafter, in step S450, theCPU 124 determines whether the user data of a super page group has beentransmitted to the RAID ECC engine 123. If yes, step S460 is performed.If no, step S420 is performed. As described above, in the embodiment,the user data of a super page group refers to the user data of K×Npages. Therefore, the CPU 124 can determine whether the K×N pages ofuser data have been transmitted to the RAID ECC engine 123 according tothe count of pages. When it is determined that the user data of the K×Npages has been transmitted to the RAID ECC engine 123, the RAID ECCengine 123 may generate K parity codes according to the user data of theK×N pages, compress the K parity codes to form the compressed K paritycodes of the user data of the super page group according to the controlsignal, and store the compressed K parity codes of the user data of thesuper page group in the RAM 1231.

Alternatively, in other embodiments, step S450 may be changed to: theRAID ECC engine 123 determines whether the K parity codes of the K×Npages of the user data are all compressed and stored in the RAM 1231. Ifyes, step S460 performed. If no, step S420 is performed. In summary,this does not affect the implementation of the invention. In addition,in other embodiments, if the management unit of the user data is asector instead of a page, the CPU 124 transmits the user data of the Nsectors to the RAID ECC engine 123 in step S420, and the RAID ECC engine123 performs the encoding operation on the N sectors of the user dataaccording to the control signal to generate a corresponding parity codein step S430, and so on, and the CPU 124 determines whether the userdata of a super sector group has been transferred to the RAID ECC engine123 in step S450. Therefore, in other embodiments, the CPU 124 can alsodetermine whether the user data of the K×N sectors have been transmittedto the RAID ECC engine 123 according to the count of sectors. When it isdetermined that the user data of the K×N sectors has been transmitted tothe RAID ECC engine 123, the RAID ECC engine 123 may generate K paritycodes according to the user data of the K×N sectors, compress the Kparity codes to form compressed K parity codes of the user data of thesuper sector group according to the control signal, and store thecompressed K parity codes of the user data of the super sector group inRAM 1231. In general, this does not affect the implementation of theinvention.

Finally, in step S460, the CPU 124 controls the RAID ECC engine 123 towrite the compressed K parity codes of the user data of the super pagegroup to the non-volatile memory 110. As described above, in theembodiment, the CPU 124 may first write the user data of the super pagegroup to the non-volatile memory 110 via the data buffer 122. After theK parity codes of the user data of the super page group are compressedand stored in the RAM 1231, the CPU 124 can control the RAID ECC engine123 to write the compressed K parity codes to the non-volatile memory110 via the page buffer 212_M (and the data buffer 122). Or, in otherembodiments, the CPU 124 may temporarily store the user data of thesuper page group in the data buffer 122. After the K parity codes of theuser data of the super page group are compressed and stored in the RAM1231, the CPU 124 can control the RAID ECC engine 123 to temporarilystore the compressed K parity codes in the data buffer 122. Then, theCPU 124 writes the user data of the super page group and the compressedK parity code of the user data of the super page group to thenon-volatile memory 110 via the data buffer 122 at one time, but theinvention is not limited thereto.

In summary, the data storage device and the parity code processingmethod provided by the embodiments of the invention may reduce theamount of data by compressing the parity code, and store the compressedparity code in the memory of the RAID ECC engine first instead ofimmediately writing the parity code generated by each encoding operationto the non-volatile memory of the data storage device. After theplurality of parity codes of the user data of an entire super page groupare compressed and stored in the memory of the RAID ECC engine, the RAIDECC engine writes the compressed plurality of parity codes to thenon-volatile memory at one time. As such, the frequency of switching thestate of the RAID ECC engine and the number and time of writing data tonon-volatile memory are reduced, thereby relatively increasing theservice life of the non-volatile memory. In addition, in the embodimentof the invention, the compression operation of the previous parity codeand the encoding operation of the user data of the next page group maybe processed in parallel to prevent the overall system performance fromdegrading.

The above description is only embodiments of the invention, and is notintended to limit the scope of the invention.

What is claimed is:
 1. A data storage device, comprising: a non-volatilememory; and a controller, electrically coupled to the non-volatilememory and comprising: an access interface, coupled to a host and thenon-volatile memory; a central processing unit (CPU), used to interpretwrite/read commands issued by the host and control the access interfaceto access user data of the non-volatile memory; and a redundant array ofindependent disks (RAID) error correcting code (ECC) engine, coupled tothe non-volatile memory and used to perform an error correctionprocedure on the user data, wherein the error correction procedure isdivided into an encoding operation or a decoding operation, the RAID ECCengine has a memory, wherein after completing the encoding operation oneach N pages of the user data to generate a corresponding parity code,the RAID ECC engine compresses the parity code and stores the compressedparity code in the memory, wherein after all K parity codes of the K×Npages of the user data are compressed and stored in the memory, the RAIDECC engine writes the compressed K parity codes to the non-volatilememory, wherein K and N are both positive integers greater than one. 2.The data storage device according to claim 1, wherein the controllerfurther comprises: a data buffer, coupled to the access interface, theRAID ECC engine and the non-volatile memory, wherein the data buffer isused to temporarily store the user data from the host or thenon-volatile memory.
 3. The data storage device according to claim 2,wherein the RAID ECC engine further comprises: a control register,coupled to the CPU and used to receive at least one control signal andtemporary data from the CPU; and a plurality of operational circuits,wherein each of the plurality of operational circuits comprises: anexclusive OR (XOR) logical operation unit; a page buffer; and a firstselector, having two input ends and an output end, wherein the two inputends of the first selector are respectively coupled to an output end ofthe XOR logical operation unit and the control register, the output endof the first selector is coupled to the page buffer, wherein the CPUcontrols, by the control register, the first selector to determine aninput source of the page buffer, so that the page buffer is used tostore an operation result from the XOR logical operation unit or used tostore the temporary data from the CPU.
 4. The data storage deviceaccording to claim 3, wherein the RAID ECC engine further comprises: astate machine, coupled to the control register and used to control theRAID ECC engine to perform the encoding operation or the decodingoperation; and a second selector, having a plurality of output ends andan input end, wherein the plurality of output ends of the secondselector are respectively coupled to input ends of the plurality ofoperational circuits, the input end of the second selector is coupled tothe data buffer or the non-volatile memory, wherein the CPU controls thesecond selector by the control register, so that the user data receivedby the input end of the second selector from the data buffer or thenon-volatile memory is outputted to at least one of the specifiedplurality of operational circuits.
 5. A parity code processing methodexecuted by a controller of a data storage device, wherein the datastorage device further comprises a non-volatile memory electricallycoupled to the controller, the controller comprises an access interface,a CPU and a RAID ECC engine, the access interface is coupled to a hostand the non-volatile memory, the CPU is used to interpret write/readcommands issued by the host and control the access interface to accessuser data of the non-volatile memory, and the parity code processingmethod comprises: configuring the CPU to issue at least one controlsignal to the RAID ECC engine and transmitting the user data of aplurality of pages to the RAID ECC engine; configuring the RAID ECCengine to perform an encoding operation on the user data of N pagesbased on the control signal to generate a corresponding parity code,compress the parity code, and store the compressed parity code in amemory of the RAID ECC engine; configuring the CPU to determine whetherthe user data of a super page group has been transmitted to the RAID ECCengine, wherein the user data of the super page group is referred to asthe user data of K×N pages; and when it is determined that the user dataof the super page group has been transmitted to the RAID ECC engine,configuring the CPU to control the RAID ECC engine to write compressed Kparity codes of the user data of the super page group to thenon-volatile memory, wherein K and N are both positive integers greaterthan one.
 6. The parity code processing method according to claim 5,wherein the controller further comprises: a data buffer, coupled to theaccess interface, the RAID ECC engine and the non-volatile memory,wherein the data buffer is used to temporarily store the user data fromthe host or the non-volatile memory.
 7. The parity code processingmethod according to claim 6, wherein the RAID ECC engine comprises: acontrol register, coupled to the CPU and used to receive at least onecontrol signal and temporary data from the CPU; and a plurality ofoperational circuits, wherein each of the plurality of operationalcircuits comprises: an XOR logical operation unit; a page buffer; and afirst selector, having two input ends and an output end, wherein the twoinput ends of the first selector are respectively coupled to an outputend of the XOR logical operation unit and the control register, theoutput end of the first selector is coupled to the page buffer, whereinthe CPU controls, by the control register, the first selector todetermine an input source of the page buffer, so that the page buffer isused to store an operation result from the XOR logical operation unit,or used to store the temporary data from the CPU.
 8. The parity codeprocessing method according to claim 7, wherein the RAID ECC enginefurther comprises: a state machine, coupled to the control register andused to control the RAID ECC engine to perform the encoding operation ora decoding operation; and a second selector, having a plurality ofoutput ends and an input end, wherein the plurality of output ends ofthe second selector are respectively coupled to input ends of theplurality of operational circuits, the input end of the second selectoris coupled to the data buffer or the non-volatile memory, wherein theCPU controls the second selector by the control register, so that theuser data received by the input end of the second selector from the databuffer or the non-volatile memory is outputted to at least one of thespecified plurality of operational circuits.